This article needs additional citations for verification. (August 2011)
The program status word[a] (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360 and its successors, and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit.
Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.
Contained within the PSW are the two bit condition code, representing zero, positive, negative, overflow, and similar flags of other architectures' status registers. Conditional branch instructions test this encoded as a four bit value, with each bit representing a test of one of the four condition code values, 23 + 22 + 21 + 20. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask value 2 selects code 2, and mask value 1 selects code 3.)
The 64-bit PSW describes (among other things)
- Interrupt masks
- Privilege states
- Condition code
- Instruction address
In the early instances of the architecture (System/360 and early System/370), the instruction address was 24[b] bits; in later instances (XA/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.
In the present instances of the architecture (z/Architecture), the instruction address is 64 bits and the PSW itself is 128 bits.
The PSW may be loaded by the LOAD PSW instruction (LPSW or LPSWE). Its contents may be examined with the Extract PSW instruction (EPSW).
S/370 Extended Architecture (S/370-XA)
Enterprise Systems Architecture (ESA)
- The nomenclature varies among architectures.
- However, a 360/67 equipped with the Extended Dynamic Address Translation feature has a 32-bit mode selected by bit 4 of the PSW in Extended PSW mode (Control Register 6, bit 8).
- Bit 22 is renamed as HFP exponent underflow in ESA/390
- Bit 23 is renamed as HFP significance in ESA/390
- S390-ESA. sfn error: no target: CITEREFS390-ESA (help)
- func67, p. 57, Glossary.
- func67, p. 15, Instruction Fetching and Execution.
- func67, p. 16, Table 4. Control Registers.
- S360, p. 15, Program Status Word.
- S360, pp. 15-16, Interruption.
- S370, pp. 15-16, Interruption.
- S370, p. 156, Instruction-Length Code.
- func67, pp. 15-16, Instruction Fetching and Execution.
- S360, p. 156, Instruction-Length Code.
- S370, pp. 4-8 – 4-9, Program-Status Word Format in BC Mode.
- S370, pp. 6-3 – 6-5, Interruption Action.
- S370, pp. 6-7 – 6-9, Instruction-Length Code.
- S370, pp. 4-6 – 4-7, Program-Status Word Format in EC Mode.
- S370-XA, p. 4-5, Program-Status-Word Format.
- S370-ESA, p. 4-5, Program-Status-Word Format.
- S390-ESA, p. 4-5, Program-Status-Word Format. sfn error: no target: CITEREFS390-ESA (help)
- z, pp. 4-5 – 4-8, Program-Status-Word Format.
- z, p. 4-8, Short PSW Format.
- IBM System/360 Principles of Operation (PDF) (Eighth ed.). IBM. September 1968. A22-6821-7.
- IBM System/360 Model 67 Functional Characteristics (PDF) (Third ed.). IBM. February 1972. GA27-2719-2.
- IBM System/370 Principles of Operation (PDF) (Eleventh ed.). IBM. September 1987. A22-7000-10.
- IBM System/370 Extended Architecture Principles of Operation (PDF) (Second ed.). IBM. January 1987. SA22-7085-1.
- IBM Enterprise Systems Architecture/370 Principles of Operation (PDF) (First ed.). IBM. August 1988. SA22-7200-0.
- z/Architecture Principles of Operation (PDF) (Thirteenth ed.). IBM. September 2019. SA22-7832-12.