An AI accelerator is a class of microprocessor or computer system designed as hardware acceleration for artificial intelligence applications, especially artificial neural networks, machine vision and machine learning. Typical applications include algorithms for robotics, internet of things and other data-intensive or sensor-driven tasks. They are often manycore designs and generally focus on low-precision arithmetic, novel dataflow architectures or in-memory computing capability. A number of vendor-specific terms exist for devices in this category, and it is an emerging technology without a dominant design.
- 1 History of AI acceleration
- 2 Nomenclature
- 3 Examples
- 4 Potential applications
- 5 See also
- 6 References
- 7 External links
History of AI acceleration
Computer systems have frequently complemented the CPU with special purpose accelerators for specialized tasks, known as coprocessors. Notable application-specific hardware units include video cards for graphics, sound cards, graphics processing units and digital signal processors. As deep learning and artificial intelligence workloads rose in prominence in the 2010s, specialized hardware units were developed or adapted from existing products to accelerate these tasks.
As early as 1993, digital signal processors were used as neural network accelerators e.g. to accelerate optical character recognition software. In the 1990s, there were also attempts to create parallel high-throughput systems for workstations aimed at various applications, including neural network simulations. FPGA-based accelerators were also first explored in the 1990s for both inference and training. ANNA was a neural net CMOS accelerator developed by Yann LeCun.
Heterogeneous computing refers to incorporating a number of specialized processors in a single system, or even a single chip, each optimized for a specific type of task. Architectures such as the cell microprocessor have features significantly overlapping with AI accelerators including: support for packed low precision arithmetic, dataflow architecture, and prioritizing 'throughput' over latency. The Cell microprocessor was subsequently applied to a number of tasks including AI.
Use of GPU
Graphics processing units or GPUs are specialized hardware for the manipulation of images and calculation of local image properties. The mathematical basis of neural networks and image manipulation are similar, embarrassingly parallel tasks involving matrices, leading GPUs to become increasingly used for machine learning tasks. As of 2016[update], GPUs are popular for AI work, and they continue to evolve in a direction to facilitate deep learning, both for training and inference in devices such as self-driving cars. GPU developers such as Nvidia NVLink are developing additional connective capability for the kind of dataflow workloads AI benefits from. As GPUs have been increasingly applied to AI acceleration, GPU manufacturers have incorporated neural network specific hardware to further accelerate these tasks. Tensor cores are intended to speed up the training of neural networks.
Use of FPGAs
Deep learning frameworks are still evolving, making it hard to design custom hardware. Reconfigurable devices such as field-programmable gate arrays (FPGA) make it easier to evolve hardware, frameworks and software alongside each other.
Microsoft has used FPGA chips to accelerate inference. The application of FPGAs to AI acceleration motivated Intel to acquire Altera with the aim of integrating FPGAs in server CPUs, which would be capable of accelerating AI as well as general purpose tasks.
Emergence of dedicated AI accelerator ASICs
While GPUs and FPGAs perform far better[quantify] than CPUs for AI related tasks, a factor of up to 10 in efficiency may be gained with a more specific design, via an application-specific integrated circuit (ASIC). These accelerators employ strategies such as optimized memory use and the use of lower precision arithmetic to accelerate calculation and increase throughput of computation. Some adopted low-precision floating-point formats used AI acceleration are half-precision and the bfloat16 floating-point format.
In-memory computing architectures
This section needs expansion. You can help by adding to it. (October 2018)
In June 2017, IBM researchers announced an architecture in contrast to the von Neumann architecture based on in-memory computing and phase-change memory arrays applied to temporal correlation detection, intending to generalize the approach to heterogeneous computing and massively parallel systems. In October 2018, IBM researchers announced an architecture based on in-memory processing and modeled on the human brain's synaptic network to accelerate deep neural networks. The system is based on phase-change memory arrays.
As of 2016, the field is still in flux and vendors are pushing their own marketing term for what amounts to an "AI accelerator", in the hope that their designs and APIs will become the dominant design. There is no consensus on the boundary between these devices, nor the exact form they will take; however several examples clearly aim to fill this new space, with a fair amount of overlap in capabilities.
In the past when consumer graphics accelerators emerged, the industry eventually adopted Nvidia's self-assigned term, "the GPU", as the collective noun for "graphics accelerators", which had taken many forms before settling on an overall pipeline implementing a model presented by Direct3D.
Stand alone products
- Google Tensor processing unit is an accelerator specifically designed by Google for its TensorFlow framework, which is extensively used for convolutional neural networks. It focuses on a high volume of 8-bit precision arithmetic. The initial first generation from 2015 focused on inference, while the second generation announced in May 2017 increased capability for neural network training also. The third-generation TPU was announced on 8 May 2018. On July 2018 the Edge TPU was announced. Edge TPU is Google’s purpose-built ASIC chip designed to run its TensorFlow Lite machine learning (ML) models at the edge.
- Adapteva epiphany is a many-core coprocessor featuring a network on a chip scratchpad memory model, suitable for a dataflow programming model, which should be suitable for many machine learning tasks.
- Intel Nervana NNP (Neural Network Processor) (a.k.a. ”Lake Crest”), which Intel claims is the first commercially available chip with a purpose built architecture for deep learning. Facebook was a partner in the design process.
- Movidius Myriad 2 is a many-core VLIW AI accelerator complemented with video fixed function units.
- Mobileye's EyeQ is a processor specialized for vision processing for self-driving cars
- NM500 is the latest as of 2016 in a series of accelerator chips for radial basis function neural nets from General Vision.
GPU based products
- Nvidia Tesla is Nvidia's line of GPU derived products marketed for GPGPU and AI tasks.
- Nvidia Volta is a microarchitecture which augments the Graphics processing unit with additional 'tensor units' targeted specifically at accelerating calculations for neural networks
- Nvidia GeForce 20 series is the first series based on the Turing microarchitecture and features built in "Tensor Cores".
- Nvidia DGX-1 is a Nvidia workstation/server product which incorporates Nvidia brand GPUs for GPGPU tasks including machine learning.
- Nvidia Tegra Xavier SoC features their Deep Learning Accelerator (DLA) and Programmable Vision Accelerator (PVA).
- Radeon Instinct is AMD's line of GPU derived products for AI acceleration.
- Qualcomm's Adreno GPUs since the Snapdragon 820 released in March 2015 using their Qualcomm Snapdragon Neural Processing Engine SDK.
- NEC SX-Aurora TSUBASA is NEC's product line for AI applications and machine learning.
AI accelerating co-processors
- Qualcomm's Hexagon DSPs since the Snapdragon 820 released in March 2015 using their Qualcomm Snapdragon Neural Processing Engine SDK.
- Cadence's Tensilica IP is a family of neural network processor and neural network-optimized digital signal processor IP core. Such as the Tensilica Vision C5 DSP released in May 2017 and Tensilica Vision Q6 DSP released in April 2018. The Tensilica DNA 100 Processor was announced in September 2018.
- Imagination Technologies' PowerVR 2NX NNA (Neural Net Accelerator) is an IP core fromlicensed for integration into chips, first announced September 2017. On December 2018 PowerVR 3NX NNA was announced.
- Apple's Neural Engine is an AI accelerator core within Apple-designed processors. The Apple A11 Bionic SoC released on September 2017 featured a dual core Neural Engine. The Apple A12 Bionic SoC released on September 2018 featured an octa core Neural Engine.
- Cambricon Technologies's Machine Learning Unit (MLU) family of neural processors such as the MLU-100 and MLU-200.
- HiSilicon's Neural Processing Unit is a neural network accelerator within HiSilicon's Kirin SoCs. The Kirin 970 with a NPU from Cambricon Technologies was released in October, 2017. The Kirin 980 with a dual core NPU from Cambricon Technologies was released in October, 2018.
- Google's Pixel Visual Core (PVC) is a fully programmable Image, Vision and AI processor for mobile devices. First featured in the Google Pixel 2 released in October, 2017.
- Arm's ML Processor is dedicated IP for neural network model inferencing acceleration. First announced as Project Trillium in January 2018.
- CEVA's NeuPro family of AI processors. The NP500, NP1000, NP2000 and NP4000 were first announced on January 2018. Each containing one programmable vector DSP and one hardwired implementation of 8-bit or 16-bit neural network layers supporting neural nets with performances ranging from 2 TOPS thru 12.5 TOPS.
- Universal Multifunction Accelerator (UMA) by Manjeera Digital Systems in Hyderabad is an accelerator in a proprietary architecture based on Middle Stratum Operations.
Research and unreleased products
- In December 2017 Tesla Motors confirmed a rumour that it is developing an AI chip for autonomous driving. Jim Keller worked on this project between at least early 2016 and early 2018.
- MIT Eyeriss is an accelerator design aimed explicitly at convolutional neural networks, using a scratchpad memory and network-on-chip architecture.
- Georgia Tech has designed a neuro-inspired processor for performing online reinforcement learning for ultra-low power robotics. It employs mixed-signal design techniques to reduce the operating power.
- Nullhop is an accelerator designed at the Institute of Neuroinformatics of ETH Zürich and University of Zürich based on sparse representation of feature maps. The second generation of the architecture is commercialized by the university spin-off Synthara Technologies.
- Kalray is an accelerator for convolutional neural nets.
- SpiNNaker is a many-core design specialized for simulating a large neural network.
- Graphcore IPU is a graph-based AI accelerator.
- DPU, by Wave Computing, a dataflow architecture
- STMicroelectronics at the start of 2017 presented a demonstrator SoC manufactured in a 28 nm process containing a deep CNN accelerator.
- TrueNorth is a manycore design based on spiking neurons rather than traditional arithmetic.
- Intel Loihi is an experimental neuromorphic chip.
- BrainChip in September 2017 introduced a commercial PCI Express card with a Xilinx Kintex Ultrascale FPGA running neuromorphic neural cores applying pattern recognition on 600 video images per second using 16 watts of power.
- IIT Madras is designing a spiking neuron accelerator for big-data analytics.
- Several memristor-based AI accelerators have been proposed which leverage in-memory computing capability of memristor.
- AlphaICs is designing an agent-based coprocessor called Real AI Processor (RAP) to enable perception and decision making in a chip.
- Autonomous vehicles: Nvidia has targeted their Drive PX-series boards at this space.
- Military robots
- Agricultural robots, for example pesticide-free weed control.
- Voice control, e.g. in mobile phones, a target for Qualcomm Zeroth.
- Machine translation
- Unmanned aerial vehicles, e.g. navigation systems, e.g. the Movidius Myriad 2 has been demonstrated successfully guiding autonomous drones.
- Industrial robots, increasing the range of tasks that can be automated, by adding adaptability to variable situations.
- Health care, to assist with diagnoses
- Search engines, increasing the energy efficiency of data centers and ability to use increasingly advanced queries.
- Natural language processing
- "Intel unveils Movidius Compute Stick USB AI Accelerator". 2017-07-21.
- "Inspurs unveils GX4 AI Accelerator". 2017-06-21.
- "Google Developing AI Processors".Google using its own AI accelerators.
- "A Survey of ReRAM-based Architectures for Processing-in-memory and Neural Networks", S. Mittal, Machine Learning and Knowledge Extraction, 2018
- "convolutional neural network demo from 1993 featuring DSP32 accelerator".
- "design of a connectionist network supercomputer".
- "The end of general purpose computers (not)".This presentation covers a past attempt at neural net accelerators, notes the similarity to the modern SLI GPGPU processor setup, and argues that general purpose vector accelerators are the way forward (in relation to RISC-V hwacha project. Argues that NN's are just dense and sparse matrices, one of several recurring algorithms)
- Ramacher, U.; Raab, W.; Hachmann, J.A.U.; Beichter, J.; Bruls, N.; Wesseling, M.; Sicheneder, E.; Glass, J.; Wurz, A.; Manner, R. (1995). Proceedings of 9th International Parallel Processing Symposium. pp. 774–781. CiteSeerX 10.1.1.27.6410. doi:10.1109/IPPS.1995.395862. ISBN 978-0-8186-7074-9.
- "Space Efficient Neural Net Implementation".
- "A Generic Building Block for Hopfield Neural Networks with On-Chip Learning" (PDF). 1996.
- Application of the ANNA Neural Network Chip to High-Speed Character Recognition
- "Synergistic Processing in Cell's Multicore Architecture". 2006.
- De Fabritiis, G. (2007). "Performance of Cell processor for biomolecular simulations". Computer Physics Communications. 176 (11–12): 660–664. arXiv:physics/0611201. doi:10.1016/j.cpc.2007.02.107.
- "Video Processing and Retrieval on Cell architecture". CiteSeerX 10.1.1.138.5133.
- Benthin, Carsten; Wald, Ingo; Scherbaum, Michael; Friedrich, Heiko (2006). 2006 IEEE Symposium on Interactive Ray Tracing. pp. 15–23. CiteSeerX 10.1.1.67.8982. doi:10.1109/RT.2006.280210. ISBN 978-1-4244-0693-7.
- "Development of an artificial neural network on a heterogeneous multicore architecture to predict a successful weight loss in obese individuals" (PDF).
- Kwon, Bomjun; Choi, Taiho; Chung, Heejin; Kim, Geonho (2008). 2008 5th IEEE Consumer Communications and Networking Conference. pp. 1030–1034. doi:10.1109/ccnc08.2007.235. ISBN 978-1-4244-1457-4.
- Duan, Rubing; Strey, Alfred (2008). Euro-Par 2008 – Parallel Processing. Lecture Notes in Computer Science. 5168. pp. 665–675. doi:10.1007/978-3-540-85451-7_71. ISBN 978-3-540-85450-0.
- "Improving the performance of video with AVX". 2012-02-08.
- "microsoft research/pixel shaders/MNIST".
- "how the gpu came to be used for general computation".
- "imagenet classification with deep convolutional neural networks" (PDF).
- "nvidia driving the development of deep learning". 2016-05-17.
- "nvidia introduces supercomputer for self driving cars". 2016-01-06.
- "how nvlink will enable faster easier multi GPU computing". 2014-11-14.
- "A Survey on Optimized Implementation of Deep Learning Models on the NVIDIA Jetson Platform", 2019
- Harris, Mark (May 11, 2017). "CUDA 9 Features Revealed: Volta, Cooperative Groups and More". Retrieved August 12, 2017.
- "FPGA Based Deep Learning Accelerators Take on ASICs". The Next Platform. 2016-08-23. Retrieved 2016-09-07.
- "microsoft extends fpga reach from bing to deep learning". 2015-08-27.
- Chung, Eric; Strauss, Karin; Fowers, Jeremy; Kim, Joo-Young; Ruwase, Olatunji; Ovtcharov, Kalin (2015-02-23). "Accelerating Deep Convolutional Neural Networks Using Specialized Hardware" (PDF). Microsoft Research.
- "A Survey of FPGA-based Accelerators for Convolutional Neural Networks", Mittal et al., NCAA, 2018
- "Google boosts machine learning with its Tensor Processing Unit". 2016-05-19. Retrieved 2016-09-13.
- "Chip could bring deep learning to mobile devices". www.sciencedaily.com. 2016-02-03. Retrieved 2016-09-13.
- "Deep Learning with Limited Numerical Precision" (PDF).
- Rastegari, Mohammad; Ordonez, Vicente; Redmon, Joseph; Farhadi, Ali (2016). "XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks". arXiv:1603.05279 [cs.CV].
- Khari Johnson (2018-05-23). "Intel unveils Nervana Neural Net L-1000 for accelerated AI training". VentureBeat. Retrieved 2018-05-23.
...Intel will be extending bfloat16 support across our AI product lines, including Intel Xeon processors and Intel FPGAs.
- Michael Feldman (2018-05-23). "Intel Lays Out New Roadmap for AI Portfolio". TOP500 Supercomputer Sites. Retrieved 2018-05-23.
Intel plans to support this format across all their AI products, including the Xeon and FPGA lines
- Lucian Armasu (2018-05-23). "Intel To Launch Spring Crest, Its First Neural Network Processor, In 2019". Tom's Hardware. Retrieved 2018-05-23.
Intel said that the NNP-L1000 would also support bfloat16, a numerical format that’s being adopted by all the ML industry players for neural networks. The company will also support bfloat16 in its FPGAs, Xeons, and other ML products. The Nervana NNP-L1000 is scheduled for release in 2019.
- "Available TensorFlow Ops | Cloud TPU | Google Cloud". Google Cloud. Retrieved 2018-05-23.
This page lists the TensorFlow Python APIs and graph operators available on Cloud TPU.
- Elmar Haußmann (2018-04-26). "Comparing Google's TPUv2 against Nvidia's V100 on ResNet-50". RiseML Blog. Retrieved 2018-05-23.
For the Cloud TPU, Google recommended we use the bfloat16 implementation from the official TPU repository with TensorFlow 1.7.0. Both the TPU and GPU implementations make use of mixed-precision computation on the respective architecture and store most tensors with half-precision.
- Tensorflow Authors (2018-02-28). "ResNet-50 using BFloat16 on TPU". Google. Retrieved 2018-05-23.
- Joshua V. Dillon, Ian Langmore, Dustin Tran, Eugene Brevdo, Srinivas Vasudevan, Dave Moore, Brian Patton, Alex Alemi, Matt Hoffman, Rif A. Saurous (2017-11-28). TensorFlow Distributions (Report). arXiv:1711.10604. Bibcode:2017arXiv171110604D. Accessed 2018-05-23.
All operations in TensorFlow Distributions are numerically stable across half, single, and double floating-point precisions (as TensorFlow dtypes: tf.bfloat16 (truncated floating point), tf.float16, tf.float32, tf.float64). Class constructors have a validate_args flag for numerical assertsCS1 maint: Multiple names: authors list (link)
- Abu Sebastian; Tomas Tuma; Nikolaos Papandreou; Manuel Le Gallo; Lukas Kull; Thomas Parnell; Evangelos Eleftheriou (2017). "Temporal correlation detection using computational phase-change memory". Nature Communications. 8. arXiv:1706.00511. doi:10.1038/s41467-017-01481-9.
- "A new brain-inspired architecture could improve how computers handle data and advance AI". American Institute of Physics. 2018-10-03. Retrieved 2018-10-05.
- Carlos Ríos; Nathan Youngblood; Zengguang Cheng; Manuel Le Gallo; Wolfram H.P. Pernice; C David Wright; Abu Sebastian; Harish Bhaskaran (2018). "In-memory computing on a photonic platform". arXiv:1801.06228 [cs.ET].
- "NVIDIA launches the World's First Graphics Processing Unit, the GeForce 256".
- Kundu, Kishalaya (2018-07-26). "Google Announces Edge TPU, Cloud IoT Edge at Cloud Next 2018". Beebom. Retrieved 2019-02-02.
- Kampman, Jeff (17 October 2017). "Intel unveils purpose-built Neural Network Processor for deep learning". Tech Report. Retrieved 18 October 2017.
- "Intel Nervana Neural Network Processors (NNP) Redefine AI Silicon". Retrieved 20 October 2017.
- "The Evolution of EyeQ".
- "NM500, Neuromorphic chip with 576 neurons".
- "Nvidia goes beyond the GPU for AI with Volta".
- "The NVIDIA Turing GPU Architecture Deep Dive: Prelude to GeForce RTX". AnandTech.
- "nvidia dgx-1" (PDF).
- Frumusanu, Andrei. "Investigating NVIDIA's Jetson AGX: A Look at Xavier and Its Carmel Cores". www.anandtech.com. Retrieved 2019-02-02.
- Smith, Ryan (12 December 2016). "AMD Announces Radeon Instinct: GPU Accelerators for Deep Learning, Coming in 2017". Anandtech. Retrieved 12 December 2016.
- "On-Device AI with Qualcomm Snapdragon Neural Processing Engine SDK". Qualcomm Developer Network. Retrieved 2019-02-02.
- "NEC SX-Aurora TSUBASA".
- "AI Acceleration-with-NEC's New Vector Computer".
- "Cadence Unveils Industry's First Neural Network DSP IP for Automotive, Surveillance, Drone and Mobile Markets".
- Frumusanu, Andrei. "Cadence Announces Tensilica Vision Q6 DSP". www.anandtech.com. Retrieved 2019-02-02.
- Frumusanu, Andrei. "Cadence Announces The Tensilica DNA 100 IP: Bigger Artificial Intelligence". www.anandtech.com. Retrieved 2019-02-02.
- "The highest performance neural network inference accelerator".
- Oh, Nate. "Imagination Announces PowerVR Series9XTP, Series9XMP, and Series9XEP GPU Cores". www.anandtech.com. Retrieved 2019-02-02.
- "The iPhone X's new neural engine exemplifies Apple's approach to AI". The Verge. Retrieved 2017-09-23.
- Cutress, Ian. "Cambricon, Makers of Huawei's Kirin NPU IP, Build A Big AI Chip and PCIe Card". www.anandtech.com. Retrieved 2019-02-02.
- "HUAWEI Reveals the Future of Mobile AI at IFA 2017".
- Cutress, Ian. "Hot Chips 2018: Arm's Machine Learning Core Live Blog". www.anandtech.com. Retrieved 2019-02-02.
- "A Family of AI Processors for Deep Learning at the Edge".
- Manjeera Digital System, UMA. "Universal Multifunction Accelerator". Manjeera Digital Systems. Retrieved 28 June 2018.
- Manjeera Digital Systems, Universal Multifunction Accelerator. "Revolutionise Processing". Indian Express. Retrieved 28 June 2018.
- AI Chip, UMA (10 May 2018). "AI Chip from Hyderabad" (News Paper). Telangana Today. Retrieved 28 June 2018.
- Lambert, Fred (December 8, 2017). "Elon Musk confirms that Tesla is working on its own new AI chip led by Jim Keller".
- Chen, Yu-Hsin; Krishna, Tushar; Emer, Joel; Sze, Vivienne (2016). "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks". IEEE International Solid-State Circuits Conference, ISSCC 2016, Digest of Technical Papers. pp. 262–263.
- "Mixed-signal Processing Powers Bio-mimetic CMOS Chip to Enable Neural Learning in Autonomous Micro-Robots | IEN".
- Aimar, Alessandro; et al. (2017). "NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps". arXiv:1706.01406 [cs.CV].
- "Synthara Technologies".
- "kalray MPPA" (PDF).
- "Graphcore Technology".
- "Wave Computing's DPU architecture". 2017-08-23.
- "A 2.9 TOPS/W Deep Convolutional Neural Network SoC in FD-SOI 28nm for Intelligent Embedded Systems" (PDF).
- "yann lecun on IBM truenorth".argues that spiking neurons have never produced leading quality results, and that 8-16 bit precision is optimal, pushes the competing 'neuflow' design
- "IBM cracks open new era of neuromorphic computing".
TrueNorth is incredibly efficient: The chip consumes just 72 milliwatts at max load, which equates to around 400 billion synaptic operations per second per watt — or about 176,000 times more efficient than a modern CPU running the same brain-like workload, or 769 times more efficient than other state-of-the-art neuromorphic approaches
- "Intel's New Self-Learning Chip Promises to Accelerate Artificial Intelligence".
- "BrainChip Accelerator".
- "India preps RISC-V Processors - Shakti targets servers, IoT, analytics".
The Shakti project now includes plans for at least six microprocessor designs as well as associated fabrics and an accelerator chip
- "drive px".
- "design of a machine vision system for weed control" (PDF).
- "qualcomm research brings server class machine learning to every data devices". October 2015.
- "movidius powers worlds most intelligent drone". 2016-03-16.