The Amber processor core is an ARM architecture-compatible 32-bit reduced instruction set computing (RISC) processor. It is open source, hosted on the OpenCores website, and is part of a movement to develop a library of open source hardware projects.
The Amber core is fully compatible with the ARMv2a instruction set and is thus supported by the GNU toolchain. This older version of the ARM instruction set is supported because it is not covered by patents, and so can be implemented with no license from ARM Holdings, unlike some prior open source projects (e.g., nnARM). The cores were developed in Verilog 2001 and are optimized for field-programmable gate array (FPGA) synthesis. For example, there is no reset logic: all registers are reset as part of FPGA initialization. The Amber project provides a complete embedded field-programmable gate array (FPGA) system incorporating the Amber core and several peripherals, including universal asynchronous receiver/transmitters (UARTs), timers, and an Ethernet MAC.
The Amber project provides two versions of the core. Both cores implement the same instruction set architecture (ISA) and are fully software compatible.
- The Amber 23 has a 3-stage pipeline, a unified instruction and data cache, a Wishbone interface, and is capable of 0.75 DMIPS (Dhrystone) per MHz. The Amber 23 core is a very small 32-bit core that performs well. Register-based instructions execute in one cycle, except for those involving multiplication. Load and store instructions require three cycles. The core's pipeline is stalled either when a cache miss occurs, or when the core performs a Wishbone access.
- The Amber 25 has a 5-stage pipeline, separate data and instruction caches, a Wishbone interface, and is capable of 1.0 DMIPS per MHz. The Amber 25 core provides 30 to 40% better performance than the Amber 23 core and is 30 to 40% larger. Register-based instructions execute in one cycle, except for instructions involving multiplication, or complex shift operations. Load and store instructions also execute in one cycle unless there is a register conflict with a following instruction. The core's pipeline is stalled when a cache miss occurs in either cache, when an instruction conflict is detected, when a complex shift is executed, or when the core performs a Wishbone access.
Both cores have been verified by booting a Linux 2.4 kernel. Versions of the Linux kernel from the 2.4 branch and earlier contain configurations for the supported ISA. Versions of the Linux kernel 2.6 and later do not explicitly support the ARM v2a ISA and so need more modifications to run. The cores do not contain a memory management unit (MMU) so they can only run a non-virtual memory variant of Linux, such as μClinux.
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