|Designed by||ARM Holdings|
|Max. CPU clock rate||to 3.0 GHz in phones and 3.3 GHz in tablets/laptops|
|L1 cache||128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core|
|L2 cache||256–512 KiB|
|L3 cache||1–4 MiB|
|Architecture and classification|
|Products, models, variants|
|Product code name(s)|
The ARM Cortex-A77 is a microarchitecture implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. The Cortex-A77 is a 4-wide decode out-of-order superscalar design with a new 1.5K macro-OP (MOPs) cache. The instruction fetch is 6-wide (up from 4-wide). The backend is 12 execution ports with a pipeline depth of 13 stages and the execution latencies of 10 stages.
The Cortex-A77 serves as the successor of the Cortex-A76. The core supports unprivileged 32-bit applications, but privileged applications must utilize the 64-bit ARMv8-A ISA. It also supports Load acquire (LDAPR) instructions (ARMv8.3-A), Dot Product instructions (ARMv8.4-A), PSTATE Speculative Store Bypass Safe (SSBS) bit instructions (ARMv8.5-A).
ARM announced 23% and 35% increases respectively in integer and floating point performance. Memory bandwidth increased 15% relative to the A76.
The Cortex-A77 is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
- Frumusanu, Andrei. "Arm's New Cortex-A77 CPU Micro-architecture: Evolving Performance". www.anandtech.com. Retrieved 2019-06-16.
- Schor, David (2019-05-26). "Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance". WikiChip Fuse. Retrieved 2019-06-16.
- "ARM documentation set for Cortex-A77". infocenter.arm.com. Retrieved 2019-06-16.